Semiconductor device
US6747356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0191
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Control of the characteristic impedance of wirings is performed with high accuracy. Relative to a first wiring of a second wiring layer arranged above a through hole of a core layer in a package board, the thickness of a first insulating layer between a first wiring layer on the surface of the core layer and the second wiring layer is made large, and the thickness of a second insulating layer between a third wiring layer that is a plane layer on the side of opposite thereto and the second wiring layer is made small, thereby allowing for: reducing the impedance coupling between the power plane of the first wiring layer on the surface of the core layer and the first and second wirings; reinforcing the impedance coupling between the power plane of the third wiring layer on the side opposite thereto and the first and second wirings; and achieving the reduction of the difference in the characteristic impedance between the first wiring arranged just above the through hole and the second wiring arranged away from just above the through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.