CMI signal timing recovery
US6748027B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4912
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for recovering a clock signal from a Coded Marked Inversion (CMI) encoded signal. A delay and divide circuit receives an incoming CMI encoded signal and produces a signal that has transitions corresponding to the bit boundaries of the CMI signal. This signal is then passed through a clock recovery loop (i.e., a phase-locked loop) to synchronize a clock signal with a CMI signal. The clock recovery loop further includes a delay circuit that adjusts the timing of the feedback signal such that it matches the delay of the CMI signal that occurs as the CMI signal passes through the delay and divide circuit. Accordingly, the circuit adjusts the timing of the recovered clock signal until it matches the clocking of the incoming CMI signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.