Digital broadcasting receiver
US6748037B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | May 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0095
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit (6) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit (92) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit (94) calculates the polarity of the error frequency. A step frequency control circuit (96) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.