Mixer noise reduction technique
US6748204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | May 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention a mixer circuit noise reduction technique is provided. The mixer circuit of the present invention includes a gain stage for receiving a first signal and producing an output signal. The mixer circuit also includes a bias circuit coupled to the gain stage through a common node for providing a bias current to the gain stage, the bias circuit having an input for receiving a second signal, and in accordance therewith, varying the bias current. Additionally, the mixer circuit includes a frequency dependent current shunt circuit coupled between the common node and a reference voltage, wherein a first portion of the bias current frequency components within a first frequency range are coupled to the reference voltage by the shunt circuit, and a second portion of the bias current frequency components within a second frequency range are coupled to the reference voltage by the shunt circuit, the first portion being larger than the second portion. As a result, the noise in the mixer circuit is reduced while the gain is enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.