Storage array having multiple erasure correction and sub-stripe writing
US6748488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe. Multiple erasure correction is also contemplated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.