Method and apparatus for managing memory operations in a data processing system using a store buffer
US6748493B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1998 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.