Systems and methods for buffering memory transactions
US6748497B1 · kind B1 · utility
7Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for memory transaction buffering are implemented. Read and write buffer units are provided. The read buffer unit is configured for storing at least one data value read from a memory device, and the write buffer unit is configured for storing at least one data value for writing to the memory device. The read buffer unit is operable for updating with the at least one data value for writing to the memory device in response to a write to the write buffer unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.