Microprocessor with instruction for saturating and packing data
US6748521B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Jun 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated results in a selected destination register. A first 32-bit operand (600) and a second 32-bit operand (602) are treated as four 16-bit fields and the sixteen bits in each field are saturated separately. Multi-field saturation circuitry is operable to treat a source operand as a number of fields, such that a multi-field saturated (610) result is produced that includes a number of saturated results each corresponding to each field. One instruction is provided which treats an operand pair as having two packed fields, and another instruction is provided that treats the operand pair has having four packed fields. Saturation circuitry is operable to selectively treat a field as either a signed value or an unsigned value. In another embodiment, an operand size different from 32-bits may be operated on, and the number of fields may be different than two or four.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.