Computer peripheral device that remains operable when central processor operations are suspended
US6748548B2 · kind B2 · utility
22Cited by
11References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | May 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.