Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
US6748549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Feb 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.