Performance monitor system and method suitable for use in an integrated circuit
US6748558B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.