System and method for adjusting timing parts
US6748565B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An exemplary embodiment of the invention is a method and apparatus for configuring system cycle time in a data processing system with at least one master latch clock generating a master latch clock signal and at least one slave latch clock generating a slave latch clock signal. Timing errors are detected during system hardware testing. Adjustments to the system timing are calculated based on error for at least one of a master latch clock signal and a slave latch clock signal. The on-cycle edge of at least one of the master latch clock signal and slave latch clock signal is adjusted based on the calculations while maintaining a corresponding mid-cycle edge of at least one of the master latch clock signal and the slave latch clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.