Method of using filler metal for implementing changes in an integrated circuit design
US6748579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.