Systems and methods for electrically isolating portions of wafers
US6750516B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems for electrically isolating portions of wafers are provided. A representative system includes a first wafer and a first conductor formed at least partially through the first wafer. A first conductor insulating layer is formed at least partially through the first wafer. The first conductor insulating layer engages the first conductor and is disposed between the first conductor and material of the first wafer. A first outer insulating layer also is provided that is formed at least partially through the first wafer. The first outer insulating layer is spaced from the first conductor insulating layer. Both the first conductor insulating layer and the first outer insulating layer are formed of dielectric material. Methods also are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.