High speed current mode logic gate circuit architecture
US6750681B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit logic topology or architecture suitable for low voltage differential logic operating at radio frequencies is disclosed. The topology, referred to as enhanced pseudo common mode logic, is similar to and compatible with traditional CML, and provides the additional advantage of eliminating the need for level conversion between consecutive logic gates, thereby increasing the potential maximum operating frequency of subsystems implemented using the invention. The invention retains most of the advantages of traditional CML, and in addition permits the independent selection of output logic high level and output logic low level so that they may be matched with the succeeding circuit input levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.