Clock generation circuits and methods with minimal glitch generation and systems using the same
US6750693B1 · kind B1 · utility
15Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2003 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which compares divide ratio control data with a count generated by the counter and generates an active state of a control signal in response. An output flip-flop toggles in response to the control signal and a selected edge of the received dock signal to toggle a state of an output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.