Offset compensated differential amplifier
US6750704B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2003 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Jan 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.