Method and design for improved fragment processing
US6750869B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 13, 2000 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Nov 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system thereof for processing data in a computer graphics system. More specifically, an anti-aliasing buffer architecture for processing fragments in a computer graphics system is described. When a new fragment for a particular pixel location is received, the fragment stack for that pixel location is read from fragment memory. The new fragment is appended to the fragment stack, and the resultant fragment stack is written back to fragment memory before it is processed in a computer graphics pipeline. Fragments stored in fragment memory are not sorted according to their distance from the view plane (the z-dimension); instead, z-ordered depth sorting is performed in the computer graphics pipeline. Using an occlude command, occluded (blocked) fragments can be deleted from the fragment stack before the fragment stack is passed to the computer graphics pipeline. The computer graphics pipeline calculates a pixel color for each pixel location. Multiple computer graphics pipelines can be executed in parallel, and the pixel colors determined in each pipeline are interleaved and stored in a frame buffer. Because fragment stacks are read from and written back to fragment memory be…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.