Arrangement of integrated circuits in a memory module
US6751113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Mar 14, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.