Semiconductor memory device
US6751154B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2003 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Mar 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a memory cell configured with two transistors and one capacitor; two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell; two address latch circuits for latching a first address signal to select one of the word drivers, the two address latch circuits being respectively provided upstream from the two word drivers; and an address decoder for decoding a second address signal to generate the first address signal. In this device, the address decoder supplies the first address signal in common to both of the two address latch circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.