Integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and for outputting both ATM and packet data
US6751224B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5665
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.