Dynamic adjustment to preserve signal-to-noise ratio in a quadrature detector system
US6751272B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1998 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/142
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a system that demodulates a frequency modulated signal using a quadrature detector circuit, an apparatus that tunes the output signal to compensate for any offset in the signal includes an offset adjustment circuit and a control circuit. The offset adjustment circuit is operably coupled to the control circuit which may consist of a DAC and a digital logic such as a computer CPU. The control circuit determines a correction signal in response to a sequence of sampled of the system output, and supplies the correction signal to the offset adjustment circuit. The offset adjustment circuit provides an offset correction signal in response to the correction signal, and combines the offset correction signal with the output of the quadrature detector to provide an offset adjusted signal at an output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.