Loop error detector for use in a PN code timing tracking loop
US6751278B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7085
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A loop error detector for use in a Pseudo Noise (PN) code timing tracking loop is disclosed. A first multiplexer receives an early I-channel signal and an early Q-channel signal, and alternately selects the received early I and Q-channel signals at a ½-chip period. A first accumulator accumulates the early I and Q-channel signals multiplexed by the first multiplexer for a specific chip period. A second multiplexer receives a late I-channel signal and a late Q-channel signal, and alternately selects the received late I and Q-channel signals at a ½-chip period. A second accumulator accumulates the late I and Q-channel signals multiplexed by the second multiplexer for the specific chip period. An operator calculates a sum and a difference of the early and late I-channel signals accumulated by the first and second accumulators, calculates a sum and a difference of the early and late Q-channel signals, and multiplies the sums by the differences. An adder adds values obtained by multiplying the sums by the differences and outputs the added value as a loop error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.