Scalable multiprocessor system and cache coherence method
US6751710B2 · kind B2 · utility
12Cited by
1References
54Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 11, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Jun 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.