Method and apparatus for instruction fetching
US6751724B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute instructions and to fetch instructions from a memory (208) according to a fetch size. This data processor (202) comprises a first input (212) to receive instructions, control logic (402) to decode the instructions, and an instruction pipeline (400) coupled to the first input (212) and the control logic (400). The instruction pipeline (400) is responsive to a first signal (214) to set the fetch size to one of a first size and a second size. The data processor (202) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.