First level cache parity error inject
US6751756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2000 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Apr 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.