Delay circuit and semiconductor device using the same
US6753707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes an output circuit including first and second output elements. The first and second output elements are connected serially between a first power supply source and a second power supply source. The delay circuit further includes a delay element, which is coupled between a first input circuit and an output circuit to generate a first control signal that is delayed with respect to the input signal. The delay circuit still further includes a first node coupled between the delay element and one of the first and second output elements; and a second node, coupled to the other output elements to supply a second control signal having substantially no delay with respect to the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.