Digital summing phase-lock loop circuit with sideband control and method therefor
US6753711B2 · kind B2 · utility
5Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jun 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital summing phase-lock loop circuit with sideband control provides high accuracy and high speed acquisition in a multi-loop frequency synthesizer. A digital phase comparator is used to control a voltage-controlled oscillator in response to inputs from multiple external loops. An initial sweep condition is set by a sweep control circuit to provide resolution of lock ambiguities in the multiple external loops. Sideband selection may be performed by selecting on of an inverted or non-inverted output of the digital phase comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.