Sequential DC offset correction for amplifier chain
US6753727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45977
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.