Self compensating correlated double sampling circuit
US6753912B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A self-compensating correlated double sampling circuit for a pixel image signal and a method to process the same. In the circuit, the analog signal generated by the photosensor of the pixel array accessed by a row selection transistor is buffered through a source follower amplifier and coupled to a column in the array. The analog signal from the selected column line is fed through a CDS circuit which is then input to the sample and hold circuit of the ADC. The main purpose of the CDS circuit is to reduce the noise and non-uniformity caused by the non ideal effects associated with the signal path from the photosensor through the CDS circuit. This is accomplished by sampling the signal and a reference level and then performing the subtraction on the two samples and the ADC ramp through the same signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.