DRAM output circuitry supporting sequential data capture to reduce core access times
US6754120B1 · kind B1 · utility
46Cited by
5References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2003 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are memory systems designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.