Semiconductor memory
US6754126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.