Dual equalizer for use in an receiver and method of operation
US6754294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | May 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for reducing a precursor ISI signal in a receiver that receives an incoming stream of symbols distorted by intersymbol interference (ISI) includes: 1) a first forward filter for receiving the incoming stream of distorted symbols and generating a first equalized output signal (Y′k); 2) a first decision feedback equalizer (DFE) stage for receiving the Y′k signal and generating a first decided symbol sequence (Ŝk−d), wherein the first DFE stage generates from Ŝk−d a first postcursor cancellation signal that reduces postcursor ISI in the Y′k signal and generates from the Y′k signal a first symbol estimate signal (vk) in which postcursor ISI is at least partially reduced; and 3) a second decision feedback equalizer (DFE) stage for receiving the Y′k signal and generating a second decided symbol sequence (Ŝk−2d), wherein the second DFE stage comprises a soft symbol estimator that receives the vk signal and generates a soft decision sequence (Ŝ′k−d) comprising decided symbols and zero output signals, and wherein the second DFE stage generates from Ŝ′k−d a precursor cancellatio…
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