Method of protecting a circuit arrangement for processing data
US6754606B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jan 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of protecting a circuit arrangement for processing data, particularly a microprocessor, preferably a smart card controller, in which circuit arrangement, during and/or at the end of manufacturing this circuit arrangement and for the purpose of manufacturing control scan tests,a shift register chain is formed by combining memory cells of the circuit arrangement, preferably memory cells formed as flip-flops, in a predetermined configuration from these memory cells,by means of this shift register chain and/or another shift register chain formed in the circuit arrangement, arbitrary states are generated in the memory cells of the circuit arrangement and evaluated in a predetermined way for testing the functional capability of the memory cells of the circuit arrangement loaded with these states,after ending the manufacturing control scan test, the shift register chain is made unusable.By rendering a shift register chain in data-processing circuit arrangements unusable, particularly in microprocessors and preferably smart card controllers, after testing, i.e. after performing the production test(s) (i.e. the manufacturing control), it will be impossible to load undefined states …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.