Method and apparatus for performing subtraction in redundant form arithmetic
US6754689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Aug 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation.A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder. Then a result is corrected by adding an adjustment of three. This adjustment value is incorporated into the result through the carry-save adder circuit. Thus the circuit produces a valid redundant representation for the subtraction…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.