Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect
US6754737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.