Queue management system having one read and one write per cycle by using free queues
US6754742B1 · kind B1 · utility
4Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1999 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Oct 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention relates to a buffer memory, method and a buffer controller for queue management usable in an ATM switch. An object of the invention is to achieve a high frequency throughput of data cells in the buffer memory. This object is achieved by using a buffer memory which is organized as 256*(424+8) SRAM-cells. The memory is used for holding ten queues, one for each incoming channel and two free-queues containing idle cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.