Method and system for logical partitioning of cache memory structures in a partitoned computer system
US6754776B2 · kind B2 · utility
26Cited by
23References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jun 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.