Distributed fault resilient shared memory
US6754789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Sep 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory sharing techniques include providing a first device and one or more additional devices. Each device has a memory and is configured to be connected to a network. A portion of the first device memory is allocated, and may be divided into two or more first device memory segments. Each first device memory segment corresponds to a device, and at least one of the first device memory segments corresponds to an additional device. A portion of the additional device memory is allocated, and may be divided into two or more additional device memory segments. Each additional device memory segment corresponds to a device, and at least one additional device memory segment corresponds to the first device. A first device data segment is provided to the additional device, and a first device data validity indication is derived at the additional device. The first device data validity indication is associated with the first device data segment, and the additional device memory segment corresponding to the first device is updated based on the association.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.