Valid bit generation and tracking in a pipelined processor
US6754808B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Oct 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.