Memory access debug facility
US6754856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.