Gaining access to internal nodes in a PLD
US6754862B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jul 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Internal registers of a PLD are exposed for debugging using a JTAG port and a scan chain. The user of a PLD identifies registers at the source code level. These registers are automatically inserted in a scan chain. An EDA software tool provides a means of choosing a register from the electronic design. The EDA tool connects the selected register to the JTAG scan chain and passes information to the software about the location in the scan chain. The EDA tool provides for scanning of the chain under automatic or manual control. The selected nodes are extracted from the chain and displayed in a user-specified format. Registers in encrypted blocks are exposed. The vendor of the block decides which registers are of importance. Once selected, the vendor creates a “debugging” file which is delivered to the customer along with the encrypted block. The debugging file contains the names of the registers, their data type, and their symbolic values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.