Method for collapsing the prolog and epilog of software pipelined loops
US6754893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes selecting a stage of the epilog to evaluate (504) and evaluating an instruction in a reference stage. This includes identifying an instruction in the reference stage that is not present in the selected stage of the epilog (506) and determining if the identified instruction can be speculated (508). If the identified instruction can be speculated, such is noted. If the instruction cannot be speculated, it is determined whether the identified instruction can be predicated (512). If the instruction can be predicated, it is marked as needing predication (514). Next, it is determined if another instruction in the reference stage is not present in the selected stage of the epilog (510). If there is, the instruction evaluation is repeated. If there is another stage of the epilog to evaluate, the evaluation is repeated (518).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.