Shared memory access controller
US6754899B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jun 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication system comprises an input-output processor IOP (11) coupled to a plurality of network devices (10) and a protocol processor PP (12), both processors being coupled to a common memory (15). Memory access control means (16) resolves competition between the processors for memory access. Normally, if one of the two processors is accessing the memory, the memory control unit (16) allows that access to be completed before allowing the other processor to access the memory. But if data loss in a network device is imminent, the IOP, is granted a higher priority memory access, the memory access controller aborts (interrupts) any memory access by the PP, allowing the IOP to access the memory immediately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.