Differential sense latch scheme
US6756823B1 · kind B1 · utility
11Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2000 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Jun 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit including a differential sense circuit and a latch, the differential sense circuit and the latch coupled so as to form a differential sense latch such that, in operation, an electronic signal stored in the latch is retained for at least one clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.