Direct power-to-ground ESD protection with an electrostatic common-discharge line

US6756834B1 · kind B1 · utility

Assignee

• Pericom Semiconductor Corporation · US

Inventors

• Paul C. F. Tong · San Jose, US
• Siu-Weng Simon Wong · Palo Alto, US
• Ping Ping Xu · San Jose, US
• Zhi Qing Liu · San Jose, US
• Wensong Chen · San Jose, US

Key dates

• Filing date: Apr 29, 2003
• Grant date: Jun 29, 2004
• Expiry date: Apr 29, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.