Variable offset amplifier circuits and their applications
US6756841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Mar 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45574
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable offset amplifier circuit includes two differential transistor pairs and a variable current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor. The first transistors are matched in size, as are the second transistors. The bias terminals of the first and second transistors serve as inputs to the amplifier circuit. The output of the amplifier circuit is associated with the differential pair output nodes of only similarly sized transistors, such that loads at the output of the amplifier circuit are sourced with current only from similarly sized transistors of the transistor pairs. The variable current generators may be adjusted to create offset in the output of amplifier circuit. The amplifier circuit has applications in a comparator circuit that also has a regenerative latch circuit, and as a sense amplifier in a receiver of a communications system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.