Memory cell structural test
US6757209B2 · kind B2 · utility
1Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.