Communication bus architecture for interconnecting data devices using space and time division multiplexing and method of operation
US6757244B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/567
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
There is disclosed, for use in a communication device, such as an access concentrator, that performs high-speed data transfers between a group of M data drivers and a group of N data receivers, a space and time division multiplexing (STDM) bus interface in which each bus line is a single source/multidrop line that connects the output of only one driver to multiple receivers (i.e., a 1:N configuration). The disclosed invention minimizes the number of data reflections on each bus line by eliminating all but one of the stubs associated with the bus drivers. The disclosed device also eliminates a single point or failure situation. The bus interface also provides additional robustness by means of a “back-up” bus line that is coupled to alternate outputs on all data drivers and to inputs on all receivers (i.e., multisource/multidrop or M:N configuration).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.