High-speed coordinated multi-channel elastic buffer
US6757348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2001 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Oct 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for enabling data transfers over communications links having a plurality of transmission lanes. In one embodiment, a system comprises a plurality of elastic buffers, each of which is coupled to one of the lanes in the communications link, and a buffer controller coupled to the buffers. Data is clocked into the elastic buffers using a first clock signal and is clocked out of the buffers by a second clock signal. The buffer controller is configured to monitor each of the buffers and to detect impending underflow or overflow conditions. In response to detect in one of these conditions, the buffer controller will cause the words to be added or deleted, respectively, to all of the elastic buffers rather than only the buffer in which the overflow/underflow condition was detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.